Founding Engineer - Physical Design

As a Founding Engineer - Physical Design, you will own critical RTL-to-GDSII steps (floorplanning, power planning, placement, CTS, routing) and drive signoff and timing closure across corners. You will lead top-level integration across hierarchical blocks, optimize power integrity and SI/PI interactions, and automate EDA flows with Tcl, Python, and Nix. You will troubleshoot congestion, crosstalk, and routing-driven timing, while collaborating across hardware and software teams to deliver tapeouts on advanced nodes (≤7nm). A strong background in VLSI, mixed-signal/digital IC design, and signoff fundamentals (STA, DRC/LVS/antenna/erc) is required, along with experience in industry tools (Innovus/ICC2, PrimeTime, StarRC/Quantus, Calibre, OpenROAD) and constraint/methodology work (SDC, MMMC, clocking strategies). This is an on-site role; expect a fast-paced, high-impact environment shaping the future of AI compute.